Quantum computers must grow from performing a few hundred error-free quantum operations (Quops) today to a trillion error-free operations (TeraQuops) to achieve their full potential.
This challenge applies equally to every quantum computer, regardless of the underlying technology they use to process and store quantum information.
The paper “A real-time, scalable, fast and highly resource efficient decoder for a quantum computer” is now available on arXiv, awaiting peer review. It explains how Riverlane’s latest quantum decoder balances the speed, accuracy, cost, hardware and power requirements to provide a practical route to error-corrected quantum computing.
No other implementations of a quantum decoder have balanced these metrics so successfully.
In short, this is the most powerful quantum decoder available today.
Real hardware, real results
The arXiv paper presents the results of a full hardware implementation of a decoding algorithm.
Our decoder - called DD1 - uses a new algorithm called Collision Clustering to achieve the right balance between speed and hardware resource utilization.
We not only decode fast enough to keep up with a superconducting quantum computer, but also only use a tiny resource footprint at the same time.
This has a significant impact within the quantum computer where the high-performance, small-area, small-power features of our decoder provide:
- Easy integration: if hardware companies use FPGAs for their control systems, our IP only occupies a small fraction of the space available on the FPGA. Also, we use industry-standard protocols for interfacing with the decoder.
- Low-power consumption: our decoder uses less than 10 mW, which is a small fraction of the typical 1W power budget in the fridges where some of these chips must operate. This means that it is possible to place our decoder in the fridge, close to the qubits. This minimises the communication latency, allowing quantum error correction to run faster than if it the decoder were outside of the fridge.
This full implementation is significant: many earlier papers have either not done an implementation (and only provided extrapolated results) or have done a partial implementation (and extrapolated from there). While such work provides us with useful approximations, ours is the first to demonstrate concretely high-performance at a small hardware resource cost.
The right balance
Until now, the scientific community has tended to focus either on solving the speed problem (for superconducting qubits) or improving accuracy (applicable to all quantum hardware types) for quantum decoders.
Often, these solutions stray towards the extreme of solving a specific problem. For example, they may either focus on speed but at significant hardware resource cost or try to be highly accurate at the cost of being too slow.
Our paper balances speed and accuracy with the other resource requirements for practical, error-corrected quantum computing. For a distance 23 rotated planar surface code and a circuit level noise probability of 0.1%, our quantum decoder can execute under 1µs with a threshold of 0.7%, while occupying less than a 0.06mm2 of area on a silicon chip and consuming less than 8mW of power.
Our decoder can be used with superconducting, trapped ion and neutral atom quantum computers. We will continue to partner with quantum hardware companies to improve and validate our decoder with plans to test on live hardware in Q4 2023.
These partnerships are key to helping the quantum community push forward, perform real-time decoding, and complete every step towards fault-tolerant computing. If you’re interested in partnering with Riverlane, contact us here.