Technical update
Introducing the world’s first low-latency QEC experiment
There are two very real requirements for quantum error correction (QEC) at scale: we need real-time QEC on real hardware. Riverlane demonstrated low-latency feedback with a scalable FPGA decoder integrated into the control system of one of Rigetti’s superconducting quantum processors.
Press release
Riverlane Releases New Report to Accelerate Industry through the ‘QEC Era’
Technical update
Introducing the world’s first low-latency QEC experiment
Technical update
Resetting our ideas on qubit resets for scalable quantum error correction
Press release
Riverlane raises $75 million to meet surging global demand for quantum error correction technology
Blog
Designing quantum computers with energy-efficiency in mind
Technical update
Riverlane’s updated decoder unlocks unlimited quantum memory experiments
Press release
Riverlane Partners with Atlantic Quantum to Advance Quantum Error Correction on Fluxonium Architecture
Blog
Introducing Riverlane’s Quantum Error Correction roadmap
Press release
Riverlane unveils three-year Quantum Error Correction roadmap
Blog
How to develop the Quantum Error Correction Stack for every qubit
Technical update
Introducing Ambiguity Clustering: the qLDPC decoder up to 150x faster than BP-OSD
Press release
Riverlane Joins the Quantum Energy Initiative
Press release
Riverlane and Alice & Bob Join Forces to Accelerate Quantum Error Correction
Press release
Riverlane awarded £2.1m by Horizon Europe to develop the next generation of its quantum error correction decoder
Press release
Riverlane awarded DARPA Quantum Benchmarking Program grant
Technical update
How the soft side of qubits hardens our QEC capabilities
Technical update
New research to help scientists unlock error-resilient early quantum use cases
Technical update