Technical update
Introducing the world’s first low-latency QEC experiment
There are two very real requirements for quantum error correction (QEC) at scale: we need real-time QEC on real hardware. Riverlane demonstrated low-latency feedback with a scalable FPGA decoder integrated into the control system of one of Rigetti’s superconducting quantum processors.
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Engineering Error Correction: Riverlane patent reduces quantum’s power bills
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Riverlane granted two US “power-aware” patents
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Rolls-Royce, Riverlane and Xanadu partner to win Canada-UK quantum computing bid
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Riverlane and Rigetti Computing partner with Oak Ridge National Laboratory to work to improve HPC-Quantum integration
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Riverlane awarded contract by Rigetti Computing to deliver QEC Stack technology to the UK’s NQCC
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Riverlane’s quantum decoder granted US patent
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A Recap of UK Government's Quantum Computing Committee Session
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Riverlane and MIT collaborate for U.S. Department of Energy program
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Riverlane named winners of the Fujitsu Quantum Simulator Challenge
Technical update
Error-free quantum chemistry edges closer in new experiment
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Riverlane publishes new research testing quantum algorithm on real quantum processor
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NQCC, Rolls-Royce and Riverlane partner to accelerate materials discovery
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Engineering Quantum Error Correction: How our no-code low power compression unlocks fault tolerant operations
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Riverlane partners with Infleqtion and Nüvü Camēras to help quantum computers ‘see’ their qubits
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Why qubits need quantum error correction (and vice versa)
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No PhD required: What the Riverlane Graduate Scheme is really like
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QEC23 Talk: A real time, scalable, fast and highly resource-efficient quantum decoder
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