Technical update
Introducing the world’s first low-latency QEC experiment
There are two very real requirements for quantum error correction (QEC) at scale: we need real-time QEC on real hardware. Riverlane demonstrated low-latency feedback with a scalable FPGA decoder integrated into the control system of one of Rigetti’s superconducting quantum processors.
Press release
Riverlane wins UK government contract to assess how current quantum computers will scale to fault tolerance
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QEC23: Six key takeaways on the state of quantum error correction
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Moonshots, Massive ROIs and Tiny Chips: Riverlane’s NQTS 2023 Highlights
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Engineering Quantum Error Correction: The Deadtime Challenge
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Parallelisation opens window to useful quantum computers for the first time
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Modelling molecules: How quantum computers simulate at the atomic level
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IEEE23: 3 Key Themes from the Riverlane Team
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Calling all classical engineers!
Press release
Riverlane Wins DeepTech Innovation Award
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Introducing the Riverlane Roadmap: Three basic steps to decoder success
Press release
Riverlane Announces World’s First Quantum Decoder Chip
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Riverlane Launches World’s Most Powerful Quantum Decoder
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Riverlane presents ‘Towards Controlling Fault-Tolerant Quantum Computers’
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Five papers pushing us towards quantum error correction
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What can you do with a quantum algorithm anyway?
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Parallel Window Decoding keynote at TQC 2023
Technical update
New quantum decoders challenge beliefs around quantum error correction
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