by Ophelia Crawford and Gyorgy Geher
Quantum error correction is a complex undertaking where many competing factors must be taken into account. One of those key balancing acts is performing error correction both fast and accurately.
As we scale quantum computers, this balancing act becomes increasingly complex. A new arXiv paper To reset, or not to reset – that is the question reveals that, as we move from memory to logical operations, our previous assumptions around resetting qubits could be incorrect.
QEC works by repeatedly measuring specific multi-qubit operators, called stabilisers, to detect errors. The measurement information is then used to correct these errors. To measure the stabilisers, syndrome extraction circuits are used, which involve extra qubits (auxiliary qubits) to help with the measurements on the main (data) qubits that hold the logical information. Typically, these auxiliary qubits are reset to the |0⟩ state after they are measured in order to begin the next round of syndrome extraction.
However, fast and accurate resetting of qubits can be difficult to achieve on physical hardware. As a result, some quantum error correction experiments on hardware were implemented without physically resetting the qubits at all.
For memory experiments, the paper confirms that resetting provides no significant benefit. But for logical operations, we find that choosing whether to reset or not impacts the performance significantly.
Our numerical simulations confirmed that resetting qubits every time can cut the time needed for fault-tolerant logical operations by up to half. This is because it allows twice as many measurement misclassification errors to be tolerated.
However, the no-reset method performs better if the reset takes too long or is not accurate enough. Therefore, deciding whether to use reset or not depends on the specifics of the hardware itself. (You can read more about how Riverlane is building The QEC Stack across multiple hardware types here.)
We also proposed two novel syndrome extraction circuits that can reduce the time needed for no-reset methods. In particular, our simulations show that our “squeezed circuit” requires only 65% of the time of the standard no-reset syndrome extraction scheme to match its performance (seen in the right-hand side plot in the figure above).
This almost cuts the time for logical computation in half, as compared to the standard no-reset case. Our results offer practical advice for designing future experiments – and you can read the full arXiv paper here.
Note on the figure: The plot is a comparison of standard no-reset circuits and squeezed no-reset circuits. It shows that one of the novel circuits we came up with has a great benefit in reducing the time-duration of logical computation by the rate shown on the right. In the best case (purple diamonds on the right), this means we need to spend 65% of the time when compared to the standard case.