by Abbas Bracken Ziad and Joan Camps
Decoders are a core technology to solve quantum error correction (QEC) but, just like the many qubit types for the quantum computers they’re trying to help, there are many proposed decoding solutions to help crack QEC.
In a new arXiv paper, Local Clustering Decoder: a fast and adaptive hardware decoder for the surface code, we present an FPGA implementation of our Local Clustering Decoder (LCD). This solution balances both the accuracy and speed required to create a real-time decoder, paving the way for a million error-free operations (aka the MegaQuOp).
Essentially, the LCD reduces the number of physical qubits required to support a logical qubit by four times when using a leakage-dominated noise model – and while decoding in under 1μs on real hardware.
The LCD will form the heart of the Deltaflow 2, representing a major step forward on Riverlane’s roadmap. We are now integrating our LCD into Deltaflow 2 into our existing partner labs, and it will be available in new installations in early 2025.
LCD for QEC
The LCD balances speed and accuracy, both of which are required to reach fault tolerant quantum computing. Higher decoder accuracy means more of the error-correction burden is placed on the decoder, and less on the qubits, so we can do more with fewer qubits.
The speed of the decoder is another important consideration because it directly contributes to the overall clock speed of the quantum computer. If the decoder is slower than the rate of incoming data, then the backlog problem occurs. This is where the quantum error data cannot be processed fast enough to keep up with the logical computations being carried out by the qubits.
By making the decoder operate fast, we allow the quantum computer to operate at faster logical clock rates. The LCD contains two main components to achieve this balance between speed and accuracy. First, a decoding engine that allows the decoder to scale and, second, an adaptivity engine helps us deal with leakage. Leakage is a source of noise where qubits no longer occupy the |0⟩ and |1⟩ states and could, instead, move into a |2⟩ or higher state. In this paper, the adaptivity engine helps us deal with leakage. In the future, it will enable other accuracy features such as 2-pass correlated decoding and soft information.
We tested the decoder under a realistic noise model where leakage is the dominant source of noise and achieved a million error-free quantum operations with a distance 17 surface code patch. This effectively halved the code distance ‘d’ required for MegaQuOp computations in our noise model from d=33 to d=17, which is a 75% saving in the number of qubits needed.
In other words, this represents a four-fold reduction in the number of physical qubits when compared to standard non-adaptive decoding.
Our d=17 decoder also uses less than 10% of the available resources of an FPGA, whilst being comfortably within the time budget of 1μs per round of syndrome extraction.
Software decoders have, until now, been the choice when you want accuracy and flexibility. But this impacts the latency, and latency impacts the logical clock rate directly. With our LCD decoder, we show that you can have your cake and eat it. Namely, you can have a flexible hardware decoder, which is faster, has a very low latency when integrated with a control system and it is adaptive. All of these features also lay the foundation for additional features in Deltaflow 3, including even higher accuracy correlated decoding. Decoding with speed and accuracy is a complex balancing act, but this is exactly what we have achieved.
To conclude, we have demonstrated that high-accuracy real-time decoding is possible, relaxing the qubit requirements to bring forward the era of fault-tolerant quantum computation.
At Riverlane, we’ve set ourselves the goal of building the first prototype of a MegaQuOp-scale QEC stack by the end of 2026. We are calling the final product Deltaflow Mega, with intermediate releases every year. This work is an important step towards the MegaQuOp.
Deltaflow interfaces across qubit modalities, allowing Riverlane’s partners to improve the quality of their qubits while safeguarding their proprietary methods and innovations. The team recently worked with partners Rigetti to demonstrate low-latency feedback with a scalable FPGA decoder integrated into the control system of one of Rigetti’s superconducting quantum processors.
If you’re interested in getting your hands on LCD, it will be included in the next release of QEC Explorer, our toolkit for software-based decoding and experimentation.
You can read the full LCD arXiv paper here and find out more about our product roadmap here.