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We think about the quantum computing stack holistically, always keeping the end application in mind. Specialising in the chemical, materials and pharmaceutical industries, we connect enterprise applications with quantum hardware. Our partners include Astra Zeneca, Merck, Johnson Matthey and Astex. Contact us if you want to learn more.

Deltaflow Control is Riverlane’s low-level control system designed to enable physicists to maximise their hardware performance. Its main goal is to provide an impeccably designed, transparent and configurable control system for hardware partners so they can build better quantum computers faster. Deltaflow Control integrates with the other modules of Deltaflow.OS® and is designed to be flexible and accommodate a wide range of control hardware needs. The first version of Deltaflow Control is being designed for atomic (trapped ion and neutral atom) qubits. However, we are already optimising its architecture to achieve the same quality levels for superconducting qubits.

The architecture of Deltaflow Control provides quantum hardware partners and academic labs with a modular architecture that enables complex control sequences. Deltaflow Control consists of:

• The front-end. High-level applications that interface with system users to define low-level control signals and return the state of the qubits and the system.
• The mid-end. Performance-optimised, platform-agnostic software that (i) converts a compressed representation of user-defined pulses into low-level electrical signals, and (ii) compresses measurements and statistics returned from the QPU.
• The back-end. A combination of latency-optimised software and digital logic IPs guarantees synchronisation and time alignment between hundreds of electrical control signals.

The front-end consists of:

• A visual interface for developers that allows a deep understanding of all the control sequences. A real ‘what you see is what you get’ for calibrating qubits and generating quantum gates.
• A language to define the low-level controls that transparently maps into what happens at the hardware level. It provides access to all configurable IPs for additional flexibility.

The mid-end comprises the following blocks:

• A demilitarised zone (DMZ) to protect control electronics from malicious attacks. Enforces the principle of least privilege to defend your company assets.
• A calibration database and associated logic that always uses the best-known definition of pulses to control the qubits.
• A fast translation unit for converting the front-end definitions into hardware-safe low-level control sequences.
• A database manager to upload the logged traces to an external digital twin of the system.

Finally, the back-end architecture consists of the following elements:

• A CPU-based, soft real-time command pipeline between the mid-end and the hard real-time control logic (sequence manager)
• High-performance data mover digital IPs that offload the CPU from (i) transmitting new sequences to real-time actuators (real-time cores) and ii) retrieving the status of the system from the data loggers.
• Real-time cores and synchronisation units (timing and syncs) to generate nanosecond aligned sequences across multiple FPGA units.
• Data loggers to trace the internal evolution of the control stack and electronics to allow deep-tracing and automation.
• High-bandwidth actuators to generate GHz-wide amplitude/frequency modulated pulses.
• Readout logic to retrieve the status of qubits in real time.

Due to Deltaflow Control’s extensibility, it is possible to include additional FPGA accelerators or CPU routines to implement ground-breaking ideas. By connecting their accelerators to the real-time cores or to the sequence manager, companies can produce better gates, tailored diagnostics and fully corrected qubits.