Without Quantum Error Correction (QEC), quantum computers will never outperform classical systems. Yet, implementing QEC demands high-performance quantum decoders that can process errors in real-time, pushing hardware to its limits.
The stakes couldn't be higher for today's hardware decisions. As quantum systems scale, we need platforms that can handle terabytes of data whilst keeping ultra-fast processing times and ultra-low latencies.
GPUs, FPGAs, and ASICs each offer unique advantages that could dramatically accelerate our path to quantum utility. These programmable solutions deliver the throughput and responsiveness the next quantum generation demands.
So which hardware deserves investment now? The decision carries profound implications, not just for today's quantum computers, but for tomorrow's breakthroughs.
The Hardware Challenge for Quantum Error Correction
Quantum computers require high-performance classical computer systems to operate effectively. These systems provide control electronics, error correction and system-wide communication.
As quantum systems scale from today's few-hundred physical qubits to the millions needed for practical applications, the demands on these classical computing resources grow exponentially. The data processing requirements are staggering; fault-tolerant quantum computers will generate approximately 100 terabytes per second of error correction data, equivalent to Netflix's entire global streaming bandwidth.
Processing this terabyte-scale volume of data with extremely low latency (of the order of tens to hundreds of microseconds) while maintaining near-perfect accuracy is a monumental hardware challenge.
Hardware Architecture Fundamentals
The QEC landscape is being shaped by several distinct hardware architectures, each with fundamentally different approaches to computation and data processing. Understanding these architectural differences is crucial to appreciating how each technology addresses the unique challenges of QEC.
The selection of the correct hardware technology is closely linked to the underlying computing architecture. For the sake of simplicity, I'll outline three architectures, based on how they leverage memories to store data and instructions:
- Single instruction, single data: The well-known Von Neumann/Harvard architectures behind all modern CPUs leverage data and instruction memories to perform computations as a series of sequential steps.
- Single (Multiple) Instructions, Multiple (Single) Data: GPUs, vector extensions and some less common architectures exploit data or instruction redundancy (i.e., same data or same operation reused multiple times) to break a program into a mixture of parallel and serial steps, thus reducing memory accesses.
- Dataflow/Systolic arrays: In this architecture, memory is not generally part of the computational model. Data "just" flows between different parallel units that need to synchronise between them.
Now, let me examine some of the potential hardware choices that quantum computing companies currently face, highlighting the different capabilities of each.
Graphics Processing Unit (GPU)
GPUs represent a specialised parallel computing architecture that has evolved far beyond its origins in graphics rendering to become a cornerstone of modern artificial intelligence, machine learning, and high-performance computing applications.
The fundamental design principle of GPUs centres on deploying thousands of relatively simple computational cores. Modern cutting-edge devices like the NVIDIA H100, for example, contain approximately 14,500 cores, each of which is capable of executing identical instructions on different data elements simultaneously.
This architectural paradigm, known as Single Instruction, Multiple Data (SIMD), enables massive parallelism for computationally intensive workloads.
GPUs’ computational architecture is based on structures called Streaming Multiprocessors (SMs), which serve as the fundamental building blocks of parallel processing. Each SM is made up of dozens of cores along with dedicated control logic, instruction dispatch units, and most importantly, shared memory—a high-speed, low-latency cache accessible to all cores within that processing block.
This shared memory architecture enables efficient data sharing and coordination among threads executing on the same SM, facilitating complex parallel algorithms that require inter-thread communication.
The architectural philosophy of GPUs prioritises throughput over latency, making them exceptionally well-suited for workloads that can decompose into thousands of independent or loosely coupled tasks. Rather than optimising for the fastest possible execution of individual operations, GPUs achieve performance through massive parallelism and clever latency-hiding techniques.
Field-Programmable Gate Array (FPGA)
FPGAs represent a fundamentally different approach to computation, offering reconfigurable hardware that can be programmed to implement potentially any kind of algorithm by wiring (via software) small digital circuits.
An array of configurable or application logic blocks (CLBs or ALBs) lies at the heart of every FPGA, each containing lookup tables (LUTs), flip-flops, and multiplexers. Using any combination of these allows us to build virtually any digital circuit. Modern FPGAs can have millions of these tiny components, which designers can leverage in conjunction with memories and premade interfaces to make ultra-low latency designs.
The strength of the FPGA lies in its customisable fabric, which can be tailored for any application. Unlike sequential processors, such as central processing units (CPUs), FPGAs can have a parallel architecture where operations occur simultaneously across different regions of the device. The spatial parallelism available to FPGAs combined with their efficient data movement patterns, enables highly efficient and low-latency implementations of specific algorithms.
Application-Specific Integrated Circuit (ASIC)
Application-Specific Integrated Circuits (ASICs) represent the ultimate in hardware specialisation: custom-designed silicon chips optimised for specific applications.
Unlike programmable devices (FPGAs), ASICs are made using a fixed circuit approach where circuits are directly built into a silicon substrate. This approach allows for maximum optimisation, power consumption, and extremely low-latency operations.
A prime example is the Tensor Product Unit (TPU), a specialised ASIC implementation of a systolic array that minimises memory access overhead through the use of small local buffers and streamlined hardware paths. Data flows rhythmically through the array (like blood through arteries, hence the name ‘systolic’), with each processing element performing computations and passing results to neighbouring elements. This eliminates the need for complex memory hierarchies and random memory accesses during computation. Systolic arrays are particularly valuable in low-latency applications that require continuous data throughput. New data can be entered into the array while previous operations are being processed.
Figure 1: A Venn diagram showing the overlap of different compute and hardware architecture
GPUs and QEC
The recent shift in GPU usage from graphics rendering to high-performance parallel computing has enabled the use of this technology in emerging sectors in the quantum industry. As mentioned above, massive classical computation is required to run quantum applications, often requiring large amounts of data to be processed in real- time.
NVIDIA, the world leading parallel computing platform and hardware provider, has accelerated and streamlined quantum decoding, classical computing integration and quantum simulation algorithms. Their most significant contribution to the industry has been CUDA-Q: a one-of-a-kind platform which allows for the integration of QPUs, quantum emulation, GPUs and CPUs.
CUDA-Q has enabled significant speedups, notably in the QEC community with its QUDA-Q QEC library, which offers a 29-35x speedup over industry standard decoders for single-shot decoding, with additional speedups of up to 42x for high-throughput syndrome decoding scenarios.
NVIDIA has also made significant progress in enabling and accelerating quantum simulation with its cuQuantum library. This software package allows for low-level quantum circuit simulation algorithms with up to 81x faster quantum circuit simulations.
FPGAs and QEC
FPGAs are playing a central role in the advancements of QEC systems today. From syndrome extraction to error decoding and real-time communications, FPGAs’ deterministic timing and spatial parallelism have made them very well suited for this fast-paced industry.
In practical applications, our team at Riverlane has demonstrated FPGA-based decoders achieving a sub-20-microsecond latency for real-time error correction in collaboration with our quantum hardware providers, including Rigetti.
Companies such as Xanadu, IBM, and several quantum startups are also actively deploying FPGA-based solutions in their quantum control stacks, with some systems demonstrating the ability to scale to thousands of physical qubits.
The reconfigurable nature of FPGAs has proven particularly valuable during the rapid evolution of quantum hardware, allowing researchers to quickly iterate on decoding algorithms and adapt to new qubit modalities without requiring complete hardware redesigns, positioning them as a critical bridge technology as the field moves toward dedicated quantum error correction ASICs.
ASICs and QEC
ASICs are slowly emerging as solutions for implementing QEC in real-time, scalable applications.
Unlike FPGAs, which trade off performance for malleability, ASICs offer a customised and highly optimised implementation for a specific application. Their primary role in QEC lies in high-throughput syndrome decoding, where real-time classical computation must keep pace with repeated qubit measurements and feedback corrective operations within microseconds.
ASIC-based decoders for surface codes and other topological codes have been prototyped in academic and industrial settings, proving that fixed-function logic can outperform general-purpose hardware in both speed and energy efficiency.
Despite their performance benefits, ASICs remain expensive and inflexible to design, making them more suitable for mature QEC protocols. However, as quantum computing moves from lab-scale prototypes to industrial deployment, ASICs are expected to play a key role in realising scalable, fault-tolerant quantum architectures by enabling dedicated, ultra-low-latency error correction pipelines integrated directly into quantum control stacks.
Comparative Analysis
|
Feature / Metric |
CPU |
GPU |
FPGA |
ASIC |
|
Parallelism |
Low (few cores) |
Very High (1000s of threads) |
Moderate–High(custom parallel logic) |
High (task-specific pipelining) |
|
Latency: |
|
|
|
|
|
Processing |
High (software overhead) |
Moderate (kernel launch overhead) |
Low (direct hardware logic) |
Ultra-Low(optimised datapaths) |
|
Communication |
Low (direct memory access) |
High (PCIe transfers) |
Low-Moderate (depends on interface) |
Ultra-Low (integrated design) |
|
End-to-end |
Moderate-High |
Low-High (depending on dataset size) |
Low |
Ultra-Low |
|
Determinism |
Low (classical OS,unpredictable), Medium (Real- Time Operative Systems) |
Medium (shared resource model and memory access) |
High (when leveraging contention-free designs*). |
Very High (when leveragingcontention- freedesigns*). |
|
Flexibility / Reconfigur-ability |
Very High (software) |
High (programmable kernels) |
Medium-low (reconfigurable, but HDL-based) |
Very Low (fixed post- fabrication) |
|
Throughput (Decoding) |
Low–Moderate |
High for batch decoding |
Moderate–High (real-time optimised) |
Very High (dedicated decoder logic) |
|
Power Efficiency |
Moderate |
Poor–Moderate |
Moderate |
Excellent |
|
Integration Complexity |
Low (standard interfaces) |
Moderate |
High (specialised toolchains) |
Very High (requires full SoC design) |
|
Development Time & Cost |
Low |
Low–Moderate |
Moderate–High |
Very High (months–years, costly) |
|
Scalability to 1,000+ qubits |
Poor (not fast enough) |
Good (data transfer bottlenecks) |
Good (with modular design) |
Excellent (if custom- designed for scale) |
What the future holds…
The hardware technologies presented in this blog post will continue evolving and advancing as quantum computers scale from today's hundreds of qubits to the millions needed for utility.
As much as I've described these technologies as separate entities, they will most likely work together rather than compete against each other. That’s why, at Riverlane, we explore all available technologies when building our QEC Stack, Deltaflow.
The future quantum computing landscape will embrace a heterogeneous approach where GPUs, FPGAs and ASICs each contribute their unique strengths to different parts of the quantum computing stack. No single hardware architecture can handle everything from microsecond-level error correction to large-scale circuit compilation.
As quantum systems approach processing 100 terabytes per second of error correction data, hardware implementation will become the deciding factor in achieving real-time decoding and maintaining quantum computer performance.
The hardware decision choices made today will ultimately determine whether specific quantum computers reach their full potential and become the world-changing machines we’ve always envisioned.