Technical update
Introducing the world’s first low-latency QEC experiment
There are two very real requirements for quantum error correction (QEC) at scale: we need real-time QEC on real hardware. Riverlane demonstrated low-latency feedback with a scalable FPGA decoder integrated into the control system of one of Rigetti’s superconducting quantum processors.
Blog
What can you do with a quantum algorithm anyway?
Blog
Parallel Window Decoding keynote at TQC 2023
Technical update
New quantum decoders challenge beliefs around quantum error correction
Blog
What is a TeraQuop decoder?
Blog
Q2B Paris 2023 - Decoding Fault-Tolerant Quantum Computers
Technical update
Riverlane patents landmark error correction technology
Technical update
Mind the gap! New algorithm speeds up the quantum computations
Blog
How Britain can become a global leader in a world of quantum computing
Blog
QCTIP 2023 - Six scientific takeaways
Blog
The sound of quantum
Technical update
A new way to prepare qubits for quantum error correction
Blog
QCTIP 2023 - Parallel window decoding enables scalable fault tolerant quantum computation
Technical update
Helping researchers identify quantum applications for electron correlation
Technical update
Opening the gates to scalable quantum computing
Press release
Riverlane Raises £15m Series B to Advance Useful Quantum Computing
Press release
Riverlane Names Maria Maragkou as VP of Product
Technical update
New quantum algorithms pave the way for materials research on error-corrected quantum computers
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