If you relish technical challenges and want to help develop ground-breaking quantum software as part of our collaborative team, we’d love to hear from you. Take a look at our job opportunities below.
Senior DevOps Engineer
At Riverlane working as a DevOps can be loosely defined as any work that is not specifically to do with the creation of a new product. Working as part of a flexible Engineering group, you will help us improving our testing and cloud infrastructures.
In Riverlane working as a DevOps can be loosely defined as any work that is not specifically to do with the creation of a new product. Working as part of a flexible Engineering group, you will help us improve our testing and cloud infrastructures.
Python Software Engineer
You will join our Engineering team building Deltaflow.OS, a new operating system for quantum computers, and related tooling.
Quantum Computing Internship for PhD Students (Boston, USA)
Our full-time internships are designed to enable current students in a quantitative field to step out of their PhD research for a short time period and to translate their skills and expertise into an industrial setting.
You will join the interdisciplinary Discover research team, developing algorithms and research code for relevant applications for quantum computers, with a focus on quantum chemistry and solving of linear equations using quantum algorithms.
Senior Digital Design Engineer
Supporting the Head of Silicon and junior engineers, As a Senior Digital Design Engineer you will work on the complete ASIC/FPGA product development flow, starting from understanding the problem space, specifying the architecture, developing the micro-architecture, writing RTL and then taking the design through to implementation to obtain the best possible power, performance and area.
Quantum Error Correction Researcher
You will join our research team working on quantum error correction. Research projects include developing and implementing fast decoding algorithms for quantum error correction, designing novel quantum codes for different hardware architectures, and design of protocols for executing fault-tolerant quantum logic.
Digital Design Engineer
As a digital design engineer you will work on the complete ASIC/FPGA product development flow starting from understanding the problem space, specifying the architecture, developing the micro-architecture, writing RTL and then taking the design through to implementation to obtain the best possible power, performance and area.
If you are interested in one of our advertised roles, please send us an up-to-date CV and covering letter. Tell us why you’re interested in working for Riverlane, and what skills and experience you can bring to the role.
HR phone screen
We want to find out more about you, your motivations for the job and whether you align with Riverlane’s values . It’s also a chance for us to answer any questions you may have about the role or what it’s like to work at Riverlane. This interview usually takes around 45 minutes.
Technical phone screen
The hiring managers want to learn more about your technical skills and experience, and what you can contribute to the role. We’ll leave time for any questions you may have. This interview usually takes 30 minutes.
We’re interested in assessing your technical capabilities. You will have a week to produce a solution to a role-specific technical challenge. Feel free to ask questions along the way!
Technical Interview (Final Stage)
The final interview takes place at our Cambridge office or via Zoom. You’ll meet some of our technical team and a senior member of staff. We’ll discuss your solutions to the technical challenge, and the team will dig deeper into your skills and experience. You will be with us for around an hour.
We will aim to get back to you as quickly as possible with a verbal offer and send you a contract within the next week. If we don’t think you’re right for Riverlane at any stage of the process, we’ll let you know promptly. We are always happy to provide feedback.