If you relish technical challenges and want to help develop ground-breaking quantum software as part of our collaborative team, we’d love to hear from you. Take a look at our job opportunities below.

Open Roles

Senior Digital Design Engineer

Supporting the Head of Silicon and junior engineers, As a Senior Digital Design Engineer you will work on the complete ASIC/FPGA product development flow, starting from understanding the problem space, specifying the architecture, developing the micro-architecture, writing RTL and then taking the design through to implementation to obtain the best possible power, performance and area.

Job type
Full Time

Software Engineer/Senior Software Engineer

You will join our Engineering team building Deltaflow.OS, a new operating system for quantum computers. As part of the Error Correction team, you will implement software to model quantum error-correcting decoders at both functional and timing-accurate levels.

Job type
Full Time

Quantum Error Correction Researcher

You will join our research team working on quantum error correction. Research projects include developing and implementing fast decoding algorithms for quantum error correction, designing novel quantum codes for different hardware architectures, and design of protocols for executing fault-tolerant quantum logic.

Job type
Full Time

Research Software Developer/Senior Research Software Developer (USA)

You will join our physical layer team, developing the understanding of qubit performance and behavior in real world environments, and enabling control systems, quantum error correction, and system integration through modelling and testing with hardware partners.

Job type
Full Time

Research Scientist/Senior Research Scientist (USA)

You will join our physical layer team, developing the understanding of qubit performance and behavior in real world environments, and enabling control systems, quantum error correction, and system integration through modelling and testing with hardware partners.

Job type
Full Time

Digital Design Engineer

As a digital design engineer you will work on the complete ASIC/FPGA product development flow starting from understanding the problem space, specifying the architecture, developing the micro-architecture, writing RTL and then taking the design through to implementation to obtain the best possible power, performance and area.

Job type
Full Time

OUR APPLICATION PROCESS

This is very much a two way process – a chance for you to find out about Riverlane and the role, and for us to find out about you and your work background. Our recruitment process is transparent and relaxed. There is no need to dress up for the interview (we’ll be wearing jeans!).

01

Application

If you are interested in one of our advertised roles, please send us an up-to-date CV and covering letter. Tell us why you’re interested in working for Riverlane, and what skills and experience you can bring to the role.

02

HR phone screen

We want to find out more about you, your motivations for the job and whether you align with Riverlane’s values . It’s also a chance for us to answer any questions you may have about the role or what it’s like to work at Riverlane. This interview usually takes around 45 minutes.

03

Technical phone screen

The hiring managers want to learn more about your technical skills and experience, and what you can contribute to the role. We’ll leave time for any questions you may have. This interview usually takes 30 minutes.

04

Technical challenge

We’re interested in assessing your technical capabilities. You will have a week to produce a solution to a role-specific technical challenge. Feel free to ask questions along the way!

05

Technical Interview (Final Stage)

The final interview takes place at our Cambridge office or via Zoom. You’ll meet some of our technical team and a senior member of staff. We’ll discuss your solutions to the technical challenge, and the team will dig deeper into your skills and experience. You will be with us for around an hour.

06

Offer

We will aim to get back to you as quickly as possible with a verbal offer and send you a contract within the next week. If we don’t think you’re right for Riverlane at any stage of the process, we’ll let you know promptly. We are always happy to provide feedback.

Flexible Working

Connecting with each other is easy thanks to technology. However, getting face-to-face is something we value and is essential for our roles and to support our growth. We operate a hybrid working policy, with staff in the office at least three days a week, with the option to work two days from home.

Many of our staff work flexibly in other ways, including part-time. Please talk to us at interview about the flexibility you need.

Recruitment Privacy Policy

We are committed to protecting and respecting your privacy. Please check our recruitment privacy policy for more information.

Internship Scheme

Our full-time internships are designed to enable current students in a quantitative field to translate their skills and expertise into an industrial setting. Interns will have a dedicated supervisor and work on a project designed to make the best use of their background and skills whilst developing their knowledge of quantum computing. We will support all interns to try and produce a concrete output by the end of the internship e.g. a paper, product, or software tool.

Riverlane offers two internship schemes, one aimed at undergraduate and master’s students, and another aimed at PhD students. Both schemes are now currently closed for 2022, and will re-open in early 2023. Full details can be found on our internships page.