Riverlane is the world's first quantum engineering company. We are hardware obsessed, qubit agile and commercially driven. We’re a passionate team collaboratively tackling some of humanity's biggest opportunities, from climate change to materials science and new drug discovery.
You will join our cross-disciplinary team of software developers, mathematicians, quantum information theorists, computational chemists and physicists – all world experts in their fields. Our collaborative, close-knit team has a track record of delivering high-quality R&D across the full quantum stack. As a growing company, you will have the freedom to think independently and creatively, as well as contribute to Riverlane's business development.
About the role
As a Senior Digital Design Engineer you will work on the complete ASIC/FPGA product development flow, starting from understanding the problem space, specifying the architecture, developing the micro-architecture, writing RTL and then taking the design through to implementation to obtain the best possible power, performance and area. You will also work with the research team to optimize algorithms to be accelerated using hardware and the software team for post silicon bring up and validation.
Prior knowledge of quantum computing is not required for this role.
What you will do
- Gain a good understanding of the problem we are trying to solve and how algorithms can be accelerated using specialized hardware
- Translate ideas into micro-architecture specifications
- Writing RTL with a design by construction mindset and using some of the best industry practices, integrating them into SoC and taking them through to implementation
- Support more junior engineers with your technical experience and insight.
- Support the Head of Silicon in improving best practices and in running design explorations.
- Work with the verification and validation team to ensure high quality of the design
What we need
- Proficiency in Verilog, System Verilog and constraint files.
- Proficiency in one or more standard bus protocols (AMBA, Wishbone)
- Experience with SVA and exposure to formal verification methods
- Understanding of low power techniques to reduce static and dynamic power
- Multi-design experience in flows such as RTL linting, CDC checks, DFT, STA etc
- Knowledge of C to assist firmware and SW suite bring up verification methodologies such as functional and code coverage
- Experience of using Python3 to build hardware models and to automate day to day tasks
- A good understanding of version control systems (Git) and use of continuous integration tools
- Good communication skills, attention to detail and passion to continuously improve our processes and flows
Even better if
Understanding of error correction schemes
How to apply
Please upload a CV and covering letter by clicking 'Apply Now'. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role.
If you have any queries, please contact email@example.com.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.