Hardware Verification Engineer

Riverlane’s mission is to make quantum computing useful far sooner than previously imaginable, starting an era of human progress as significant as the industrial and digital revolutions. Large and reliable quantum computers have the potential to turn fields like clean energy, drug design and aerospace upside down. We’re building the Operating System for these pioneering new machines, leading the world to tackle quantum computing’s defining challenge: error correction. We’re growing fast and making remarkable progress.

You will join the Engineering Function, focusing on the verification of our hardware IPs and SOC solutions. As part of the verification team, you will define IP, subsystem, and system level tests – to fully test our solutions. You will use state of the art techniques and tools to identify bugs in our products before they reach our users. You will work together with our hardware designers to maximize internal learnings, and quality of our processes and products.

Working as part of a the Deltaflow Control product team, you will work with our hardware designers and software embedded engineers to produce a fully verified, trusted and performant solution. As part of your role, you will:

• Work with designers and architects to define verification plan based on design specifications. Define and track detailed test plan for different block and system level.
• Implement scalable testbenches including checkers, reference models, coverage groups in system Verilog. Implement self-testing directed and random tests.
• Maintain Design verification environment, keep track of regression, coverage metrics, bugs encountered and fixed.

You do not need a background in quantum computing – we run optional training and talks for you to learn more.

• Demonstrable commercial experience
• A person that is keen to collaborate, share and can independently define the scope of work.
• Testbench design with verification frameworks like UVM/OVM.
• Knowledge of assertion (SVA) is valuable.