Cambridge, UK | Full-time | Permanent | £46,000 - £55,000
Riverlane’s mission is to make quantum computing useful far sooner than previously imaginable, starting an era of human progress as significant as the industrial and digital revolutions. Large and reliable quantum computers have the potential to turn fields like clean energy, drug design and aerospace upside down. We’re building the Operating System for these pioneering new machines, leading the world to tackle quantum computing’s defining challenge: error correction. We’re growing fast and making remarkable progress.
About the role
You will join the Engineering Function, focusing on the verification of our hardware IPs and SOC solutions. As part of the verification team, you will define IP, subsystem and system level tests – to fully test our solutions. You will use state of the art techniques and tool to identify bugs in our products before they reach our users. You will work hand-in-hand with our hardware designers to maximize internal learnings and quality of our processes and products.
What will you do
Working as part of the Deltaflow Control product team, you will work with our hardware designers and software embedded engineers to produce a fully verified, trusted and performant solution. We want to have robust verification framework where simulation and formal based verification complement each other. As part of your role, you will:
- Work with designers and architects to identify key design features for formal verification
- Create a comprehensive formal verification plan. Develop re-usable and scalable formal verification code base
- Develop, extend, maintain and improve our SVA checkers for formal and simulation use
- Track and report verification metrics and closure
- Build and maintain scripts and automated workflow for formal tools.
You do not need a background in quantum computing – we run optional trainings and talks for you to learn more.
What we need
- Commercial experience.
- Have good knowledge on formal verification concepts, methodology and tools.
- Have experience in deploying formal verification on complex designs.
- A person that is keen to collaborate, share and can independently define the scope of work.
- Have knowledge on wider verification frameworks like UVM/OVM.
How to apply
Please upload a CV and covering letter by clicking 'Apply Now'. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role.
If you have any queries, please contact firstname.lastname@example.org.
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.